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copyright 1995 by dallas semiconductor corporation. all rights reserved. for important information regarding patents and other intellectual property rights, please refer to dallas semiconductor data books. ds1992/ds1993 1kbit/4kbit memory i button tm ds1994 4kbit plus time memory i button ds1992/ds1993/ds1994 032697 1/20 special features ? 4096 bits of read/write nonvolatile memory (ds1993 and ds1994) ? 1024 bits of read/write nonvolatile memory (ds1992) ? 256bit scratchpad ensures integrity of data transfer ? memory partitioned into 256bit pages for packetizing data ? data integrity assured with strict read/write protocols ? contains real time clock/calendar in binary format (ds1994) ? interval timer can automatically accumulate time when power is applied (ds1994) ? programmable cycle counter can accumulate the number of system poweron/off cycles (ds1994) ? programmable alarms can be set to generate inter- rupts for interval timer, real time clock, and/or cycle counter (ds1994) ? write protect feature provides tamperproof time data (ds1994) ? programmable expiration date that will limit access to sram and timekeeping (ds1994) ? clock accuracy is better than 2 minute/month at 25 c (ds1994) ? operating temperature range from 40 c to +70 c ? over 10 years of data retention common i button features ? unique, factorylasered and tested 64bit registra- tion number (8bit family code + 48bit serial number + 8bit crc tester) assures absolute traceability because no two parts are alike ? multidrop controller for microlan tm ? digital identification and information by momentary contact ? chipbased data carrier compactly stores information ? data can be accessed while affixed to object ? economically communicates to bus master with a single digital signal at 16.3k bits per second ? standard 16 mm diameter and 1wire protocol ensure compatibility with i button family ? button shape is selfaligning with cupshaped probes ? durable stainless steel case engraved with registra- tion number withstands harsh environments ? easily affixed with selfstick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim ? presence detector acknowledges when reader first applies voltage ? meets ul#913 (4th edit.); intrinsically safe appara- tus, approved under entity concept for use in class i, division 1, group a, b, c and d locations f5 microcan tm 5.89 ground data 0.36 0.51 04 af 000000fbc52b yyww 16.25 17.35 registered rr all dimensions shown in millimeters. ordering information ds1992lf5 f5 microcan ds1993lf5 f5 microcan ds1994lf5 f5 microcan examples of accessories ds9096p selfstick adhesive pad ds9101 multipurpose clip ds9093ra mounting lock ring ds9093f snapin fob ds9092 i button probe
ds1992/ds1993/ds1994 032697 2/20 i button description the ds1992/ds1993/ds1994 memory i button (here- after referred to as ds199x) is a rugged read/write data carrier that acts as a localized database that can be eas- ily accessed with minimal hardware. the nonvolatile memory and optional timekeeping capability offer a sim- ple solution to storing and retrieving vital information pertaining to the object to which the i button is attached. data is transferred serially via the 1wire protocol which requires only a single data lead and a ground return. the scratchpad is an additional page that acts as a buffer when writing to memory. data is first written to the scratchpad where it can be read back. after the data has been verified, a copy scratchpad command will transfer the data to memory. this process insures data integrity when modifying the memory. a 48bit serial number is factory lasered into each ds199x to provide a guaranteed unique identity which allows for absolute traceability. the durable microcan package is highly resistant to environmental hazards such as dirt, mois- ture, and shock. its compact coinshaped profile is selfaligning with mating receptacles, allowing the ds199x to be easily used by human operators. acces- sories permit the ds199x to be mounted on almost any surface including plastic key fobs, photoid badges and printed circuit boards. applications include access control, workinprogress tracking, electronic travelers, storage of calibration constants, and debit tokens. with the optional time- keeping functions (ds1994), a real time clock/calendar, interval timer, cycle counter, and programmable inter- rupts are available in addition to the nonvolatile memory. the internal clock can be programmed to deny memory access based on absolute time/date, total elapsed time, or the number of accesses. these fea- tures allow the ds1994 to be used to create a stop- watch, alarm clock, time and date stamp, logbook, hour meter, calendar, system power cycle timer, interval timer, and event scheduler. overview the ds199x has four main data components: 1) 64-bit lasered rom, 2) 256-bit scratchpad, 3) 1024bit (ds1992) or 4096bit (ds1993 and ds1994) sram, and 4) timekeeping registers (ds1994). the timekeep- ing section utilizes an on-chip oscillator that is con- nected to a 32.768 khz crystal. the sram and time- keeping registers reside in one contiguous address space referred to hereafter as memory. all data is read and written least significant bit first. the memory functions will not be available until the rom function protocol has been established. this pro- tocol is described in the rom functions flow chart (fig- ure 9). the master must first provide one of four rom function commands: 1) read rom, 2) match rom, 3) search rom, or 4) skip rom. after a rom function sequence has been successfully executed, the memory functions are accessible and the master may then pro- vide any one of the four memory function commands (figure 6).
ds1992/ds1993/ds1994 032697 3/20 ds199x block diagram figure 1 64-bit lasered rom internal registers & counters rom function control memory function control 256-bit scratchpad sram (256bit pages) 32,768 hz oscillator data holding registers timekeeping functions parasite-powered circuitry memory lid contact note: shaded areas only present in ds1994 3v lithium
ds1992/ds1993/ds1994 032697 4/20 parasite power the block diagram (figure 1) shows the parasite-pow- ered circuitry. this circuitry astealso power whenever the data input is high. the data line will provide sufficient power as long as the specified timing and voltage requirements are met. the advantages of parasite power are two-fold: 1) by parasiting off this input, lithium is conserved and 2) if the lithium is exhausted for any reason, the rom may still be read normally. 64-bit lasered rom each ds199x contains a unique rom code that is 64 bits long. the first eight bits are a 1-wire family code. the next 48 bits are a unique serial number. the last eight bits are a crc of the first 56 bits. (see figure 2.) the 1-wire crc is generated using a polynomial gener- ator consisting of a shift register and xor gates as shown in figure 3. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the dallas 1-wire cyclic redundancy check is available in the book of ds19xx i button standards. the shift register bits are initialized to zero. then start- ing with the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, then the serial number is entered. after the 48th bit of the serial number has been entered, the shift register contains the crc value. shifting in the eight bits of crc should return the shift register to all zeros. 64-bit lasered rom figure 2 family code serial number crc 48-bit unique number 8 bits lsb msb 04h = ds1994 06h = ds1993 08h = ds1992 1-wire crc code figure 3 xor xor xor input (msb) (lsb)
ds1992/ds1993/ds1994 032697 5/20 ds1994 memory map figure 4a 0000h 0020h 0040h 0060h 0080h 00a0h 00c0h 00e0h 0100h 0120h 0140h 0160h 0180h 01a0h 01c0h 01e0h 0200h page 0 page 1 page 2 page 3 page 4 page 5 page 6 page 7 page 8 page 9 page 10 page 11 page 12 page 13 page 14 page 15 page 16 page scratchpad status register control register real-time counter registers interval time counter registers cycle counter registers real-time alarm registers interval time alarm registers cycle alarm registers page 16 timekeeping registers 0200h 0201h 0202h 0207h 020ch 0215h 021ah 0210h status register x cce ite rte ccf itf rtf x 0200h dsel stop start auto man osc ro wpc wpi wpr 0201h 76543 210 76543 210 control register memory note: each page is 32 bytes (256 bits). the hex values represent the starting address for each page or register.
ds1992/ds1993/ds1994 032697 6/20 ds1993 memory map figure 4b 0000h 0020h 0040h 0060h 0080h 00a0h 00c0h 00e0h 0100h 0120h 0140h 0160h 0180h 01a0h 01c0h 01e0h page 0 page 1 page 2 page 3 page 4 page 5 page 6 page 7 page 8 page 9 page 10 page 11 page 12 page 13 page 14 page 15 page scratchpad memory note: each page is 32 bytes (256 bits). the hex values represent the starting address for each page or register. ds1992 memory map figure 4c 0000h 0020h 0040h 0060h page 0 page 1 page 2 page 3 page scratchpad memory note: each page is 32 bytes (256 bits). the hex values represent the starting address for each page or register.
ds1992/ds1993/ds1994 032697 7/20 memory the memory map in figure 4 shows a 32byte page called the scratchpad and additional 32byte pages called memory. the ds1992 contains pages 0 though 3 which make up the 1024bit sram. the ds1993 and ds1994 contain pages 0 through 15 which make up the 4096bit sram. the ds1994 also contains page 16 which has only 30 bytes that contain the timekeeping registers. the scratchpad is an additional page that acts as a buffer when writing to memory. data is first written to the scratchpad where it can be read back. after the data has been verified, a copy scratchpad command will transfer the data to memory. this process insures data integrity when modifying the memory. timekeeping (ds1994) a 32,768 hz crystal oscillator is used as the time base for the timekeeping functions. the oscillator can be turned on or off by an enable bit in the control register. the oscillator must be on for the real time clock, interval timer and cycle counter to function. the timekeeping functions are double buffered. this feature allows the master to read time or count without the data changing while it is being read. to accomplish this, a snapshot of the counter data is transferred to holding registers which the user accesses. this occurs after the eighth bit of the read memory function com- mand. real-time clock the real-time clock is a 5-byte binary counter. it is incremented 256 times per second. the least significant byte is a count of fractional seconds. the upper four bytes are a count of seconds. the real-time clock can accumulate 136 years of seconds before rolling over. time/date is represented by the number of seconds since a reference point which is determined by the user. for example, 12:00a.m., january 1, 1970 could be a reference point. interval timer the interval timer is a 5-byte binary counter. when enabled, it is incremented 256 times per second. the least significant byte is a count of fractional seconds. the interval timer can accumulate 136 years of seconds before rolling over. the interval timer has two modes of operation which are selected by the auto/man bit in the control register. in the auto mode, the interval timer will begin counting after the data line has been high for a period of time determined by the dsel bit in the control register. similarly, the interval timer will stop counting after the data line has been low for a period of time deter- mined by the dsel bit. in the manual mode, time accu- mulation is controlled by the stop/start bit in the control register. note: for auto mode operation, the high level on the data line must be greater than or equal to 2.1 volts. cycle counter the cycle counter is a 4-byte binary counter. it incre- ments after the falling edge of the data line if the appropriate data line timing has been met. this timing is selected by the dsel bit in the control register. (see astatus/controlo section). note: for cycle counter operation, the high level on the data line must be greater than or equal to 2.1 volts. alarm registers the alarm registers for the real-time clock, interval timer, and cycle counter all operate in the same manner. when the value of a given counter equals the value in its associated alarm register, the appropriate flag bit is set in the status register. if the corresponding interrupt enable bit(s) in the status register is set, an interrupt is generated. if a counter and its associated alarm register are write protected when an alarm occurs, access to the device becomes limited. (see astatus/controlo, ainter- ruptso, and the aprogrammable expirationo sections.) status/control registers (ds1994) the status and control registers are the first two bytes of page 16 (see amemory mapo, figure 4). status register 76 5 4 3 2 1 0 0200h x x cce ite rte ccf itf rtf don't care bits read only rtf itf ccf 0 1 2 real-time clock alarm flag interval timer alarm flag cycle counter alarm flag
ds1992/ds1993/ds1994 032697 8/20 when a given alarm occurs, the corresponding alarm flag is set to a logic 1. the alarm flag(s) is cleared by reading the status register. rte ite cce 3 4 5 real-time interrupt enable interval timer interrupt enable cycle counter interrupt enable writing any of the interrupt enable bits to a logic 0 will allow an interrupt condition to be generated when its corresponding alarm flag is set (see ainterruptso sec- tion). control register wpi wpr osc auto stop start man. dsel ro wpc 76 543210 wpr wpi wpc 0 1 2 write protect real-time clock/alarm registers write protect interval timer/alarm registers write protect cycle counter/alarm registers 0201h setting a write protect bit to a logic 1 will permanently write protect the corresponding counter and alarm reg- isters, all write protect bits, and additional bits in the control register. the write protect bits can not be written in a normal manner (see awrite protect/programmable expirationo section). 3 read only ro if a programmable expiration occurs and the read only bit is set to a logic 1, then the ds1994 becomes read only. if a programmable expiration occurs and the read only bit is a logic 0, then only the 64-bit lasered rom can be accessed (see awrite protect/programmable expira- tiono section). 4 oscillator enable osc this bit controls the crystal oscillator. when set to a logic 1, the oscillator will start operation. when the oscillator bit is a logic 0, the oscillator will stop. auto/man 5 automatic/manual mode when this bit is set to a logic 1, the interval timer is in automatic mode. in this mode, the interval timer is enabled by the data line. when this bit is set to a logic 0, the interval timer is in manual mode. in this mode the interval timer is enabled by the stop/start bit. stop/start 6 stop/start (in manual mode) if the interval timer is in manual mode, the interval timer will start counting when this bit is set to a logic 0 and will stop counting when set to a logic 1. if the interval timer is in automatic mode, this bit has no effect. dsel 7 delay select bit this bit selects the delay that it takes for the cycle counter and the interval timer (in auto mode) to see a transition on the data line. when this bit is set to a logic 1, the delay time is 123 + 2 ms. this delay allows commu- nication on the data line without starting or stopping the interval timer and without incrementing the cycle counter. when this bit is set to a logic 0, the delay time is 3.5 + 0.5 ms. memory function commands the amemory function flow charto (figure 6) describes the protocols necessary for accessing the memory. an example follows the flowchart. three address registers are provided as shown in figure 5. the first two regis- ters represent a 16-bit target address (ta1, ta2). the third register is the ending offset/data status byte (e/s). the target address points to a unique byte location in memory. the first five bits of the target address (t4:t0) represent the byte offset within a page. this byte offset points to one of 32 possible byte locations within a given page. for instance, 00000b points to the first byte of a page where as 1 1111b would point to the last byte of a page. the third register (e/s) is a read only register. the first five bits (e4: e0) of this register are called the ending off- set. the ending offset is a byte offset within a page (1 of 32 bytes). bit 5 (pf) is the partial byte flag. bit 6 (of) is the overflow flag. bit 7 (aa) is the authorization accepted flag.
ds1992/ds1993/ds1994 032697 9/20 address registers figure 5 target address (ta1) target address (ta2) ending address with data status (e/s) (read only) 7543210 t7 t6 t5 t4 t3 t2 t1 t0 6 t15 t14 t13 t12 t11 t10 t9 t8 aa of pf e4 e3 e2 e1 e0 write scratchpad command [0fh] after issuing the write scratchpad command, the user must first provide the 2-byte target address, followed by the data to be written to the scratchpad. the data will be written to the scratchpad starting at the byte offset (t4:t0). the ending offset (e4: e0) will be the byte offset at which the host stops writing data. the maximum end- ing offset is 1 1111b (31d). if the host attempts to write data past this maximum offset, the overflow flag (of) will be set and the remaining data will be ignored. if the user writes an incomplete byte and an overflow has not occurred, the partial byte flag (pf) will be set. read scratchpad command [aah] this command may be used to verify scratchpad data and target address. after issuing the read scratchpad command, the user may begin reading. the first two bytes will be the target address. the next byte will be the ending offset/data status byte (e/s) followed by the scratchpad data beginning at the byte offset (t4: t0). the user may read data until the end of the scratchpad after which the data read will be all logic 1's. copy scratchpad [55h] this command is used to copy data from the scratchpad to memory. after issuing the copy scratchpad com- mand, the user must provide a 3-byte authorization pat- tern. this pattern must exactly match the data contained in the three address registers (ta1, ta2, e/s, in that order). if the pattern matches, the aa (authorization accepted) flag will be set and the copy will begin. a logic 0 will be transmitted after the data has been copied until a reset pulse is issued by the user. any attempt to reset the part will be ignored while the copy is in progress. copy typically takes 30 m s. the data to be copied is determined by the three address registers. the scratchpad data from the begin- ning offset through the ending offset, will be copied to memory, starting at the target address. anywhere from 1 to 32 bytes may be copied to memory with this com- mand. whole bytes are copied even if only partially writ- ten. the aa flag will be cleared only by executing a write scratchpad command. read memory [f0h] the read memory command may be used to read the entire memory. after issuing the command, the user must provide the 2-byte target address. after the two bytes, the user reads data beginning from the target address and may continue until the end of memory, at which point logic 1's will be read. it is important to realize that the target address registers will contain the address provided. the ending offset/data status byte is unaf- fected. the hardware of the ds1992/ds1993/ds1994 pro- vides a means to accomplish errorfree writing to the memory section. to safeguard reading data in the 1wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. such a packet would typically store a 16bit crc with each page of data to insure rapid, errorfree data trans- fers that eliminate having to read a page multiple times to determine if the received data is correct or not. (see the book of ds19xx i button standards, chapter 7 for the recommended file structure to be used with the 1wire environment.)
ds1992/ds1993/ds1994 032697 10/20 memory function flow chart figure 6 master tx memory function command 0fh write scratchpad aah read scratchpad 55h copy scratchpad f0h read memory nnn master tx ta1 (t7:t0) master rx ta1 (t7:t0) master tx ta1 (t7:t0) master tx ta2 (t15:t8) master rx ta2 (t15:t8) master tx ta2 (t15:t8) master tx ta1 (t7:t0) master tx ta2 (t15:t8) ds199x sets scratchpad offset = (t4:t0) and clears (pf of aa) master rx ending offset/data status byte (e/s) master tx e/s byte authorization code match ? aa = 1 ds199x tx a1os ds199x copies scratchpad data to memory ds199x tx a0os master tx reset ds199x sets scratchpad offset = (t4:t0) master rx data byte from scratchpad offset master tx reset scratchpad offset = 11111b master rx a1os increment scratchpad offset master tx data byte to scratchpad offset ds199x sets (e4:e0) = scratchpad offset master tx reset scratchpad offset = 11111b master tx data increment scratchpad offset partial byte written of = 1 master tx reset pf = 1 ds199x tx presence pulse (see figure 9) master tx reset ds199x sets memory address = (t15:t0) master rx data byte from memory address master tx reset increment memory address memory address = 21dh master rx a1os yyyn y y n n y y n ny n y n n y y n y n y y n y n n y
ds1992/ds1993/ds1994 032697 11/20 memory function examples example: write two data bytes to memory locations 0026h and 0027h (the seventh and eighth bytes of page 1). read entire memory. master mode data (lsb first) comments tx reset reset pulse (480960 m s) rx presence presence pulse tx cch issue askip romo command tx 0fh issue awrite scratchpado command tx 26h ta1, beginning offset=6 tx 00h ta2, address=00 26h tx <2 data bytes> write 2 bytes of data to scratchpad tx reset reset pulse rx presence presence pulse tx cch issue askip romo command tx aah issue aread scratchpado command rx 26h read ta1, beginning offset=6 rx 00h read ta2, address=00 26h rx 07h read e/s, ending offset=7, flags=0 rx <2 data bytes> read scratchpad data and verify tx reset reset pulse rx presence presence pulse tx cch issue askip romo command tx 55h issue acopy scratchpado command tx 26h ta1 tx 00h ta2 tx 07h e/s tx reset reset pulse rx presence presence pulse tx cch issue askip romo command tx f0h issue aread memoryo command tx 00h ta1, beginning offset=0 tx 00h ta2, address=00 00h rx <128 bytes (ds1992)> <512 bytes (ds1993)> <542 bytes (ds1994)> read entire memory tx reset reset pulse rx presence presence pulse, done authorization code
ds1992/ds1993/ds1994 032697 12/20 write protect/programmable expiration (ds1994) the write protect bits (wpr, wpi, wpc) provide a means of write protecting the timekeeping data and lim- iting access to the ds1994 when an alarm occurs (pro- grammable expiration). the write protect bits may not be written by performing a single copy scratchpad command. instead, to write these bits, the copy scratchpad command must be per- formed three times. please note that the aa bit will set, as expected, after the first copy command is success- fully executed. therefore, the authorization pattern for the second and third copy command should have this bit set. the read scratchpad command may be used to verify the authorization pattern. the write protect bits, once set, permanently write pro- tect their corresponding counter and alarm registers, all write protect bits, and certain control register bits as shown in figure 7. the time/count registers will con- tinue to count if the oscillator is enabled. if the user wishes to set more than one write protect bit, the user must set them at the same time. once a write protect bit is set it cannot be undone, and the remaining write pro- tect bits, if not set, cannot be set. the programmable expiration takes place when one or more write protect bits have been set and a correspond- ing alarm occurs. if the ro (read only) bit is set, only the read scratch and read memory function commands are available. if the ro bit is a logic a0o, no memory function commands are available. the rom functions are always available. write protect chart figure 7 write protect bit set: wpr wpi wpc data protected from real time clock interval timer cycle counter user modification: real time alarm interval time alarm cycle counter alarm wpr wpr wpr wpi wpi wpi wpc wpc wpc ro ro ro osc * osc * osc * stop/start ** dsel auto/man * becomes write a1o only, i.e., once written to a logic a1o, may not be written back to a logic a0o. ** forced to a logic a0o. 1-wire bus system the 1-wire bus is a system which has a single bus mas- ter and one or more slaves. in most instances the ds199x behaves as a slave. the exception is when the ds1994 generates an interrupt due to a timekeeping alarm. the discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-wire signalling (signal types and tim- ing). hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have open drain or 3state outputs. the 1-wire port of the ds199x is open drain with an internal circuit equivalent to that shown in figure 8. a multidrop bus consists of a 1wire bus with multiple slaves attached. the 1-wire bus has a maxi- mum data rate of 16.3k bits per second and requires a pull-up resistor of approximately 5 k w . the idle state for the 1-wire bus is high. if for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 120 m s, one or more of the devices on the bus may be reset.
ds1992/ds1993/ds1994 032697 13/20 hardware configuration figure 8 v cc ds199x 1-wire port r x t x 100 ohm mosfet 5 k w r x t x r x = receive t x = transmit 5 m a typ. bus master data transaction sequence the protocol for accessing the ds199x via the 1-wire port is as follows: ? initialization ? rom function command ? memory function command ? transaction/data initialization all transactions on the 1-wire bus begin with an initial- ization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds199x is on the bus and is ready to operate. for more details, see the a1-wire signallingo section. rom function commands once the bus master has detected a presence, it can issue one of the four rom function commands. all rom function commands are eight bits long. a list of these commands follows (refer to flowchart in figure 9): read rom [33h] this command allows the bus master to read the ds199x's 8-bit family code, unique 48-bit serial num- ber, and 8-bit crc. this command can only be used if there is a single ds199x on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-and result). the resultant family code and 48bit serial number will usually result in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64-bit rom sequence, allows the bus master to address a specific ds199x on a multidrop bus. only the ds199x that exactly matches the 64-bit rom sequence will respond to the subsequent memory function command. all slaves that do not match the 64-bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. skip rom [cch] this command can save time in a single drop bus sys- tem by allowing the bus master to access the memory functions without providing the 64-bit rom code. if more than one slave is present on the bus and a read command is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pull-downs will pro- duce a wire-and result). search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1wire bus or their 64bit rom codes. the search rom com- mand allows the bus master to use a process of elimina- tion to identify the 64bit rom codes of all slave devices on the bus. the search rom process is the repetition of a simple 3step routine: read a bit, read the comple- ment of the bit, then write the desired value of that bit. the bus master performs this simple, 3step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes may be identified by additional passes. see chapter 5 of the book of ds19xx i button standards for a compre- hensive discussion of a search rom, including an actual example. search interrupt [ech] (ds1994) this rom command works exactly as the normal rom search, but it will identify only devices with interrupts that have not yet been acknowledged.
ds1992/ds1993/ds1994 032697 14/20 rom functions flow chart figure 9 n y y y ds199x t x presence pulse 33h read rom command 55h match rom command f0h search rom command cch skip rom command ds199x t x family code 1 byte bit 0 match? bit 0 match? bit 1 match? bit 1 match? bit 63 match? bit 63 match? ds199x t x serial number 6 bytes ds199x t x crc byte n nn y y y nn y n n y y y ds199x t x bit 0 ds199x t x bit 0 ds199x t x bit 1 ds199x t x bit 1 ds199x t x bit 63 ds199x t x bit 63 master t x bit 1 master t x bit 0 master t x bit 0 master t x bit 1 master t x bit 63 master t x bit 63 master t x reset pulse master t x rom function command master t x memory function command (see figure 6) n n ech interrupt search y y bit 0 match? bit 1 match? bit 63 match? y y ds199x t x bit 0 ds199x t x bit 0 ds199x t x bit 1 ds199x t x bit 1 ds199x t x bit 63 ds199x t x bit 63 master t x bit 0 master t x bit 1 master t x bit 63 interrupt active n n n n n ds1994 only
ds1992/ds1993/ds1994 032697 15/20 1wire signalling the ds199x requires strict protocols to insure data integrity. the protocol consists of five types of signalling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, read data and inter- rupt pulse (ds1994). all these signals except presence pulse and interrupt pulse are initiated by the bus master. the initialization sequence required to begin any com- munication with the ds199x is shown in figure 10. a reset pulse followed by a presence pulse indicates the ds199x is ready to send or receive data given the cor- rect rom command and memory function command. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 m s). the bus master then releases the line and goes into receive mode (rx). the 1wire bus is pulled to a high state via the pullup resistor. after detecting the rising edge on the data line, the ds199x waits (t pdh , 1560 m s) and then transmits the presence pulse (t pdl , 60240 m s). there are special conditions if interrupts are enabled where the bus master must check the state of the 1wire bus after being in the rx mode for 480 m s. these conditions will be discussed in the ainterrupto section. read/write time slots the definitions of write and read time slots are illustrated in figure 11. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the ds199x to the master by triggering a delay circuit in the ds199x. during write time slots, the delay circuit determines when the ds199x will sample the data line. for a read data time slot, if a a0o is to be transmitted, the delay circuit determines how long the ds199x will hold the data line low overriding the 1 gen- erated by the master. if the data bit is a a1o, the i button will leave the read data time slot unchanged. initialization procedure areset and presence pulseso figure 10 t rsth t rstl t r v pullup v pullup min v ih min v il max 0v 480 m s < t rstl < * 480 m s < t rsth < (includes recovery time) 15 m s < t pdh < 60 m s 60 m s < t pdl < 240 m s t pdh t pdl master r x apresence pulseo master t x areset pulseo resistor master ds199x * in order not to mask interrupt signalling by other devices on the 1wire bus, t rstl + t r should always be less than 960 m s.
ds1992/ds1993/ds1994 032697 16/20 read/write timing diagram figure 11 writeone time slot 60 m s t rec t low1 v pullup v pullup min v ih min v il max 0v 60 m s < t slot < 120 m s 1 m s < t low1 < 15 m s 1 m s < t rec < 15 m s sampling window t slot i button writezero time slot v pullup v pullup min v ih min v il max 0v t slot t rec t low0 60 m s < t low0 < t slot < 120 m s 1 m s < t rec < sampling window 60 m s 15 m s i button readdata time slot v pullup v pullup min v ih min v il max 0v t slot t rec t rdv t lowr 60 m s < t slot < 120 m s 1 m s < t lowr < 15 m s 0 < t release < 45 m s 1 m s < t rec < t rdv = 15 m s t su < 1 m s t release master sampling window resistor master ds199x t su
ds1992/ds1993/ds1994 032697 17/20 interrupts (ds1994) if the ds1994 detects an alarm condition, it will automat- ically set the corresponding alarm flag in the status register. an interrupt condition begins whenever any alarm flag is set and the flag's corresponding interrupt bit is enabled. the interrupt condition ceases when the alarm flags are cleared (i.e., the interrupt is acknowl- edged by reading the status register, address 200h) or if the corresponding interrupt enable bit is disabled. the ds1994 can produce two types of interrupts: spon- taneous interrupts, called type 1, and delayed inter- rupts, type 2. spontaneous interrupts need to be armed by a reset pulse after all communication on the 1wire bus has finished. a single falling slope on the 1wire bus will disarm this type of interrupt. if an alarm condi- tion occurs while the device is disarmed, at first a type 2 interrupt will be produced. spontaneous interrupts are signalled by the ds1994 by pulling the data line low for 960 to 3840 m s as the inter- rupt condition begins (figure 12). after this long low pulse a presence pulse will follow. if the alarm condition occurs just after the master has sent a reset pulse, i.e., during the high or low time of the presence pulse, the ds1994 will not assert its interrupt pulse until the pres- ence pulse is finished (figure 13). if the ds1994 cannot assert a spontaneous interrupt, either because the data line was not pulled high, com- munication was in progress, or the interrupt was not armed, it will extend the next reset pulse to a total length of 960 to 3840 m s (delayed interrupt). if the alarm condition occurs during the reset low time of the reset pulse, the ds1994 will immediately assert its interrupt pulse; thus the total low time of the pulse can be extended up to 4800 m s (figure 14). if a ds1994 with a not previously signaled alarm detects a poweron cycle on the 1wire bus, it will send a presence pulse and wait for the reset pulse sent by the master to extend it and to subsequently issue a presence pulse (figure 15). as long as an interrupt has not been acknowledged by the master, the ds1994 will continue sending inter- rupt pulses. the interrupt signaling discussed so far is valid for the first opportunity the device has to signal an interrupt. it is not required for the master to acknowledge an interrupt immediately. if an interrupt is not acknowledged, the ds1994 will continue signaling the interrupt with every reset pulse. to do so, ds1994 devices of revision b (earlier production parts) will always use the waveform of the type 2 interrupt (figure 14). devices of revision c (latest production) will either use the waveform of the type 2 interrupt (figure 14) or the waveform of the type 1a interrupt (figure 13). the waveform of the type 2 in- terrupt will be observed after a communication to a de- vice other than the interrupting one; after successful communication to the interrupting device (without ac- knowledging the interrupt) the waveform of the type 1a interrupt will be found. the revision code of the ds1994 is branded on the lid of the microcan. the field rr (see figure on page 1), just a above the family code, will read bx for revision b and cx for revision c. (the character axo represents a 1-dig- it number that is not related to the chip inside.) the revi- sion code can also be determined indirectly by observ- ing the waveforms used for interrupt signaling. type 1 interrupt figure 12 reset pulse interrupt pulse 960 - 3840 m s presence pulse note: no communication following presence pulse., i.e. no falling edge. interrupt condition occurs here. v cc 1-wire bus gnd presence pulse line type legend: see next page.
line type legend: bus master active low both bus master and ds1994 active low ds1994 active low resistor pull-up ds1992/ds1993/ds1994 032697 18/20 type 1a interrupt (special case) figure 13 interrupt pulse 960 - 3840 m s presence pulse reset pulse interrupt condition occurs during the presence pulse, but the interrupt is not generated until the presence pulse is completed. v cc gnd 1-wire bus v ih of ds1994 presence pulse type 2 interrupt figure 14 interrupt pulse 960 - 4800 m s presence pulse interrupt condition exists prior to master releasing reset. 1-wire bus v cc gnd type 2 interrupt (special case) figure 15 presence pulse interrupt condition occurs while the bus is powered down. 1wire bus v cc gnd interrupt pulse 960 - 3840 m s presence pulse bus powers up.
ds1992/ds1993/ds1994 032697 19/20 physical specifications size see mechanical drawing weight 3.3 grams (f5 package) humidity 90% rh at 50 c altitude 10,000 feet expected service life 10 years at 25 c safety meets ul#913 (4th edit.); intrinsically safe apparatus, approved under entity concept for use in class i, division 1, group a, b, c and d locations absolute maximum ratings* voltage on any pin relative to ground 0.5v to +7.0v operating temperature 40 c to +70 c storage temperature 40 c to +70 c * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (v pup =2.8v to 6.0v, 40 c to +70 c) parameter symbol min typ max units notes logic 1 v ih 2.2 v cc +0.3 v 1 , 8 logic 0 v il 0.3 +0.8 v 1 output logic low @ 4ma v ol 0.4 v 1 output logic high v oh v pup 6.0 v 1, 2 input load current i l 5 m a 3 capacitance (t a = 25 c) parameter symbol min typ max units notes i/o (1wire) c in/out 100 800 pf 6 ac electrical characteristics (40 c to 70 c) parameter symbol min typ max units notes time slot t slot 60 120 m s write 1 low time t low1 1 15 m s write 0 low time t low0 60 120 m s read data valid t rdv exactly 15 m s release time t release 0 15 45 m s read data setup t su 1 m s 5 interrupt t int 960 4800 m s 9 recovery time t rec 1 m s reset time high t rsth 480 m s 4 reset time low t rstl 480 960 m s 7 presence detect high t pdhigh 15 60 m s presence detect low t pdlow 60 240 m s
ds1992/ds1993/ds1994 032697 20/20 notes: 1. all voltages are referenced to ground. 2. v pup = external pullup voltage. 3. input load is to ground. 4. an additional reset or communication sequence cannot begin until the reset high time has expired. 5. read data setup time refers to the time the host must pull the 1wire bus low to read a bit. data is guaranteed to be valid within 1 m s of this falling edge and will remain valid for 14 m s minimum. (15 m s total from falling edge on 1wire bus.) 6. capacitance on the data line could be 800 pf when power is first applied. if a 5 k w resistor is used to pullup the data line to v cc , 5 m s after power has been applied, the parasite capacitance will not affect normal communica- tions. 7. the reset low time (t rstl ) should be restricted to a maximum of 960 m s, to allow interrupt signalling, otherwise, it could mask or conceal interrupt pulses. 8. v ih is a function of the external pullup resistor and the v cc power supply (ds1992, ds1993 only). 9. ds1994 only.

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